The present invention relates to the problem area of clock generation circuitry, present inside a VLSI module (Chip). This clock generation circuitry needs to have control inputs that are capable of being varied in value, such that the effect that those varying values have on the clocks being generated, may be observed at the chip outputs.
The need and application for clock generation is ubiquitous. An exemplary, but not exclusive application can be found in a computing system wherein a processor utilizes a so-called system clock to communicate with external system devices such as DRAM, and synthesizes one or more internal clocks from the system clock to clock so-called functional units within the processor. It should be understood that a computing system is but one of many applications known to one skilled in the art.
By the way of further background, clock generation can be broadly categorized into either phase-locked loop (PLL) circuitry or delay line loop (DLL) circuitry. Pll circuitry generally takes reference signals, such as the system clock, compares it to the feedback signal, and generates an error signal in response thereto. The error signal drives a voltage controlled oscillator which produces an output signal. The output signal is also scaled to generate the feedback signal for comparison with the reference signal. The divisor setting of the divider sets the frequency ratio between the reference and output clock signals.
Although a review of the prior art related to test boundary scans was noted in the prior art, however no specific reference to the use of JTAG extensions, controlled and varied using JTAG design specific registers, was not found in any prior art reference.
The present invention relates to the problem area of clock generation circuitry, present inside a VLSI module (Chip). This clock generation circuitry needs to have control inputs that are capable of being varied in value, such that the effect that those varying values have on the clocks being generated, may be observed at the chip outputs. This invention solves the problem defined above by adding circuitry to part of the chip which implements IEEE Standard 1149.1 (IEEE Test Access Port and Boundary Scan Architecture, A.K.A. JTAG). Since JTAG circuitry uses clocking that is required to be independent of any other clocking domains on the chip, the requirement detailed above is met.